1. Field of the Invention
The present invention relates to memories made in the form of an array of memory cells in an integrated circuit. The present invention more specifically applies to DRAMs, that is, memories in which the reading of the content of a memory cell is performed by comparison with a precharge level.
2. Discussion of the Related Art
FIG. 1 partially and schematically shows a conventional example of a DRAM structure.
Storage elements or memory cells C(j, i) are arranged in an array. Each storage element is associated with a pair of bit lines BLdi and BLri in a column BLi (of rank i) shown vertically and with a word line (WLj) shown horizontally. The bit lines are common to columns of storage elements and the word lines are common to rows of storage elements. Each storage element C(j, i) of column i and of row j includes, between a bit line (for example, BLdi) and the ground, the series connection of a MOS transistor T and a capacitive element C. The gate of transistor T is connected to word line BLj. The bit line to which the storage element is not connected forms, for this cell, a reference or precharge line. Most often, each bit line alternately forms the precharge line of a storage element one row out of two. Each column BLi of the memory plane is associated with a sense amplifier SAi having the function of comparing the analog levels present on the bit lines in a read cycle of a storage element, for conversion into logic levels. Generally, the bit lines are precharged and an interval of a few hundreds of millivolts at most is measured by means of the comparator constitutive of the sense amplifier of the column, to differentiate a low level (0) from a high level (1).
The structure and operation of a conventional sense amplifier of DRAM cells as well as the selection and precharge elements associated therewith are known and will not be detailed.
In some applications, the logic signals provided by the sense amplifiers of a DRAM cell are combined by a wired state machine to provide a specific result. An example of such an application is the finding of image contours in graphical applications. Combinations of XOR or XNOR type are generally used to locate the contours of a digital image stored in an array of memory cells while respecting the pixel arrangement with respect to the display.
In such applications, the implementation of the logic combinations by means of wired state machines requires, for a same row, several successive combinations due to the individual reading of the memory cells in the array. The performed comparison is generally sequential, which takes time.